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r10ds0240ej0002 rev.0.02 page 1 of 29 dec. 01, 2014 preliminary datasheet rmqcha3636dgba, rmqcha3618dgba 36-mbit ddr? ii+ sram 2-word burst architecture (2.0 cycle read latency) description the rmqcha3636dgba is a 1,048,576-word by 36-bit and the rmqcha3618dgba is a 2,097,152-word by 18-bit synchronous quad data rate static ram fabricated with advanced cmos technology using full cmos six-transistor memory cell. it integrates unique synchronous periphera l circuitry and a burst counter . all input registers are controlled by an input clock pair (k and /k) and are latche d on the positive edge of k and /k. these products are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration. these produ cts are packaged in 165-pin plastic fbga package. features ? power supply z 1.8 v for core (v dd ), 1.4 v to v dd for i/o (v ddq ) ? clock z fast clock cycle time for high bandwidth z two input clocks (k and /k) for precise ddr timing at clock rising edges only z two output echo clocks (cq and /cq) simplify data capture in high-speed systems z clock-stop capability with s restart ? i/o z common data input/output bus z pipelined double data rate operation z hstl i/o z user programmable output impedance z pll circuitry for wide output data valid window and future frequency scaling z data valid pin (qvld) to indicate valid data on the output ? function z two-tick burst for low ddr transaction size z internally self-timed write control z simple control logic for easy depth expansion z jtag 1149.1 compa tible test access port ? package z 165 fbga package (13 x 15 x 1.4 mm) r10ds0240ej0002 rev.0.02 dec. 01, 2014
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 2 of 29 dec. 01, 2014 orderable part name definition column no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 example r m q x x a x xxx d g b a - 2 2 2 # a c 0 rm qch a 36 36 d g ba 22 2 # a c 0 renesas internal use pb-free tray industrial temp. ( t a = -40 to 85 ) cycle time package type quality level internal code i/o bus width memory size 1.8v v dd qdr sram / ddr sram renesas memory
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 3 of 29 dec. 01, 2014 order information orderable part name organization (word x bit) cycle time clock frequency operating ambient temperature core supply voltage (v) package rmqcha3636dgba-222#ac0 1m x 36 2.20ns 450mhz t a = ? 40 to 85c 1.8 0.1 165-pin rmqcha3636dgba-252#ac0 2.50ns 400mhz plastic bga rmqcha3618dgba-222#ac0 2m x 18 2.20ns 450mhz (13 x 15) rmqcha3618dgba-252#ac0 2.50ns 400mhz pb-free
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 4 of 29 dec. 01, 2014 pin arrangement [ rmqcha3636dgba ] 1m x 36 (top view) 1 2 3 4 5 6 7 8 9 10 11 a /cq nc sa r-/w /bw2 /k /bw1 /ld sa nc cq b nc dq27 dq18 sa /bw3 k /bw0 sa nc nc dq8 c nc nc dq28 v ss sa nc sa v ss nc dq17 dq7 d nc dq29 dq19 v ss v ss v ss v ss v ss nc nc dq16 e nc nc dq20 v ddq v ss v ss v ss v ddq nc dq15 dq6 f nc dq30 dq21 v ddq v dd v ss v dd v ddq nc nc dq5 g nc dq31 dq22 v ddq v dd v ss v dd v ddq nc nc dq14 h /doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc dq32 v ddq v dd v ss v dd v ddq nc dq13 dq4 k nc nc dq23 v ddq v dd v ss v dd v ddq nc dq12 dq3 l nc dq33 dq24 v ddq v ss v ss v ss v ddq nc nc dq2 m nc nc dq34 v ss v ss v ss v ss v ss nc dq11 dq1 n nc dq35 dq25 v ss sa sa sa v ss nc nc dq10 p nc nc dq26 sa sa qv ld sa sa nc dq9 dq0 r tdo tck sa sa sa nc sa sa sa tms tdi notes: 1. address expansion order for future higher density srams: 9a 3a 10a 2a 7a 5b. 2. nc pins can be left floating or connected to 0v to v ddq
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 5 of 29 dec. 01, 2014 [ rmqcha3618dgba ] 2m x 18 (top view) 1 2 3 4 5 6 7 8 9 10 11 a /cq nc sa r-/w /bw1 /k nc /ld sa sa cq b nc dq9 nc sa nc k /bw0 sa nc nc dq8 c nc nc nc v ss sa nc sa v ss nc dq7 nc d nc nc dq10 v ss v ss v ss v ss v ss nc nc nc e nc nc dq11 v ddq v ss v ss v ss v ddq nc nc dq6 f nc dq12 nc v ddq v dd v ss v dd v ddq nc nc dq5 g nc nc dq13 v ddq v dd v ss v dd v ddq nc nc nc h /doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc dq4 nc k nc nc dq14 v ddq v dd v ss v dd v ddq nc nc dq3 l nc dq15 nc v ddq v ss v ss v ss v ddq nc nc dq2 m nc nc nc v ss v ss v ss v ss v ss nc dq1 nc n nc nc dq16 v ss sa sa sa v ss nc nc nc p nc nc dq17 sa sa qv ld sa sa nc nc dq0 r tdo tck sa sa sa nc sa sa sa tms tdi notes: 1. address expansion order for future higher density srams: 9a 3a 10a 2a 7a 5b. 2. nc pins can be left floating or connected to 0v to v ddq
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 6 of 29 dec. 01, 2014 pin descriptions name i/o type descriptions note sa input synchronous address inputs: these inputs are registered and must meet the setup and hold times around the rising ed ge of k. these inputs are ignored when device is deselected. /ld input synchronous load: this input is brought low when a bus cycle sequence is to be defined. this definition includes addr ess and read / write direction. r-/w input synchronous read / write input: when /ld is low, this input designates the access type (read when r-/w is high, write when r-/w is low) for the loaded address. r-/w must meet the setup and hol d times around the rising edge of k. /bw x input synchronous byte writes: when low, these inputs cause their respective byte to be registered and written during write cycles. these signals are sampled on the same edge as the corresponding data and must meet setup and hold times around the rising edges of k and /k for each of the rising edge comprising the write cycle. see byte write truth table for signal to data relationship. k, /k input input clock: this input clock pair registers address and control inputs on the rising edge of k, and registers data on the rising edge of k and the rising edge of /k. /k is ideally 180 degrees out of phase with k. all synchronous inputs must meet setup and hold times around the clock rising edges. these balls cannot remain v ref level. /doff input pll disable: when low, this input causes the pll to be bypassed for stable, low frequency operation. tms tdi input ieee1149.1 test inputs: 1.8 v i/o leve ls. these balls may be left unconnected if the jtag function is not used in the circuit. tck input ieee1149.1 clock input: 1.8 v i/o levels. this ball must be tied to v ss if the jtag function is not used in the circuit. zq input output impedance matching input: this input is used to tune the device outputs to the system data bus impedance. q and cq output impedance are set to 0.2 rq, where rq is a resistor from this ball to ground. this ball can be connected directly to v ddq , which enables the minimum impedance mode. this ball cannot be connected directly to v ss or left unconnected.
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 7 of 29 dec. 01, 2014 name i/o type descriptions note dq 0 to dq n input output synchronous data i/os: input data must meet setup and hold times around the rising edges of k and /k. output data is synchronized to the k clock. the x18 device uses dq0~ dq17. dq18~dq35 should be treated as nc pin. the x36 device uses dq0 to dq35. cq, /cq output synchronous echo clock outputs: the edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. these signals run freely and do not stop when q tri-states. tdo output ieee 1149.1 test output: 1.8 v i/o level. qvld output valid output indicator: the q valid indicates valid output data. qvld is edge aligned with cq and /cq. v dd supply power supply: 1.8 v nominal. see dc characteristics and operating conditions for range. 1 v ddq supply power supply: isolated output buffer supply. nominally 1.5 v. see dc characteristics and operatin g conditions for range. 1 v ss supply power supply: ground. 1 v ref - hstl input reference voltage: nominally v ddq /2, but may be adjusted to improve system noise margin. provides a refer ence voltage for the hstl input buffers. nc - no connect: these pins can be left floating or connected to 0v to v ddq . notes: 1. all power supply and ground balls must be co nnected for proper oper ation of the device.
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 8 of 29 dec. 01, 2014 block diagram [ rmqcha3636dgba ] [ rmqcha3618dgba ] /ld /bwx k /k 72 19 36 36 dq 19 k k,/k zq 2 cq, /cq memory array e t i r w r e t s i g e r t u p t u o r e t s i g e r t u p t u o t c e l e s t u p t u o r e f f u b r e v i r d e t i r w p m a e s n e s x u m 4 r-/w 72 72 sa /ld r-/w k address registry and logic data registry and logic /k k /ld /bwx k /k 36 20 18 18 dq 20 k k,/k zq 2 cq, /cq memory array e t i r w r e t s i g e r t u p t u o r e t s i g e r t u p t u o t c e l e s t u p t u o r e f f u b r e v i r d e t i r w p m a e s n e s x u m 2 r-/w 36 36 sa /ld r-/w k address registry and logic data registry and logic /k k
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 9 of 29 dec. 01, 2014 power-up and initialization sequence - v dd must be stable before k, /k clocks are applied. - recommended voltage application sequence : v ss v dd v ddq & v ref v in . (0 v to v dd , v ddq < 200 ms) - apply v ref after v ddq or at the same time as v ddq . - then execute either one of the following three sequences. 1. single clock mode - drive /doff high (/doff can be tied high from the start). - then provide stable clocks (k, /k) for at least 20 us. 2. pll off mode (/doff tied low) - in the "nop and setup stage", provide stable clocks (k, /k) for at least 20 us. pll constraints 1. these chips use the pll. the clock input should have low phase jitter which is specified as tkc var. 2. the lower end of the frequency at wh ich the pll can operate is 250 mhz. (please refer to ac characteristics table for detail.) 3. when the operating frequency is changed or /doff level is changed, setup cycles are required again. status power up & unstable stage nop & set-up stage normal operation v dd set-up cycle v ddq v ref /doff k, /k fix high (=vddq)
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 10 of 29 dec. 01, 2014 programmable output impedance 1. output buffer impedance can be programmed by terminating the zq ball to vss through a precision resistor (rq). the value of rq is five times the output impedance desired. the allowable range of rq to guarantee impedance matching with a tolerance of 15% is between 175 and 350 . the total external capacitance of zq ball must be less than 7.5 pf. qvld (valid data indicator) 1. qvld is provided on the qdr-ii+ and ddr-ii+ to simplify data capture on high speed systems. the q valid indicates valid output data. qvld is activated half cycle before the read data for the receiver to be ready for capturing the data. qvld is in activated half cycle before the read finish for the receiver to stop capturing the data. qvld is edge aligned with cq and /cq.
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 11 of 29 dec. 01, 2014 k truth table operation k /ld r-/w dq write cycle: load address, input write data on two consecutive k and /k rising edges l l data in input data d(a+0) d(a+1) input clock k(t+1) /k(t+1) read cycle: load address, output read data on two consecutive c and /c rising edges l h data out output data q(a+0) q(a+1) input clock k(t+2) /k(t+2) nop (no operation) h x high-z standby (clock stopped) stopped x x previous state notes: 1. h: high level, l: low level, : don?t care, : rising edge. 2. data inputs are registered at k and /k rising edges. data outputs are delivered at k clock edges. 3. /ld and r-/w must meet setup/hold times around the rising edges (low to high) of k and are registered at the rising edge of k. 4. this device contains circuitry that will ensure the outputs will be in high-z during power-up. 5. refer to state diagram and timi ng diagrams for clarification. 6. when clocks are stopped, the following cases are recomme nded; the case of k = low, /k = high, or the case of k = high, /k = low. this condition is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 12 of 29 dec. 01, 2014 byte write truth table ( x 36 ) operation k /k /bw0 /bw1 /bw2 /bw3 write d0 to d35 - l l l l - l l l l write d0 to d8 - l h h h - l h h h write d9 to d17 - h l h h - h l h h write d18 to d26 - h h l h - h h l h write d27 to d35 - h h h l - h h h l write nothing - h h h h - h h h h notes: 1. h: high level, l: low level, : rising edge. 2. assumes a write cycle was initiated. /bwx can be altered for any portion of the burst write operation provided that the setup and hold requirements are satisfied. byte write truth table ( x 18 ) operation k /k /bw0 /bw1 write d0 to d17 - l l - l l write d0 to d8 - l h - l h write d9 to d17 - h l - h l write nothing - h h - h h notes: 1. h: high level, l: low level, : rising edge. 2. assumes a write cycle was initiated. /bwx can be altered for any portion of the burst write operation provided that the setup and hold requirements are satisfied.
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 13 of 29 dec. 01, 2014 bus cycle state diagram notes: 1. bus cycle is terminated at the end of this sequence (burst count = 2). 2. state machine control timing se quence is controlled by k. nop write double count = count + 2 load new address count = 0 power up /ld = h supply voltage provided /ld = l r-/w = l /ld = l & count = 2 /ld = h & count = 2 read double count = count + 2 r-/w = h /ld = l & count = 2 /ld = h & count = 2
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 14 of 29 dec. 01, 2014 electrical characteristics absolute maximum ratings parameter symbol rating unit notes input voltage on any ball v in ? 0.5 to v dd + 0.5 (2.5 v max.) v 1,4 input/output voltage v i/o ? 0.5 to v ddq + 0.5 (2.5 v max.) v 1,4 core supply voltage v dd ? 0.5 to 2.5 v 1,4 output supply voltage v ddq ? 0.5 to v dd v 1,4 junction temperature tj +125 (max) c 5 storage temperature t stg ? 55 to +125 c notes: 1. all voltage is referenced to v ss . 2. permanent device damage may occur if absolute ma ximum ratings are exceeded. functional operation should be restricted the operation conditions. exposu re to higher than recommended voltages for extended periods of time could affect device reliability. 3. these cmos memory circuits have been designed to m eet the dc and ac specifications shown in the tables after thermal equilibrium has been established. 4. the following supply voltage application sequence is recommended: v ss , v dd , v ddq , v ref then v in . remember, according to the absolute maximum ratings table, v ddq is not to exceed 2.5 v, whatever the instantaneous value of v ddq . 5. some method of cooling or airflow should be considered in the system. recommended dc operating conditions parameter symbol min typ max unit notes power supply voltage -- core v dd 1.7 1.8 1.9 v 1 power supply voltage -- i/o v ddq 1.4 1.5 v dd v 1,2 input reference voltage -- i/o v ref 0.68 0.75 0.95 v 3 input high voltage v ih (dc) v ref + 0.1 - v ddq + 0.3 v 1,4,5 input low voltage v il (dc) -0.3 - v ref - 0.1 v 1,4,5 notes: 1. at power-up, v dd and v ddq are assumed to be a linear ramp from 0v to v dd (min.) or v ddq (min.) within 200ms. during this time, v ddq < v dd and v ih < v ddq . during normal operation, v ddq must not exceed v dd . 2. please pay attention to tj not to exceed the temperature shown in the absolute maximum ratings table due to current from v ddq . 3. peak to peak ac com ponent superimposed on v ref may not exceed 5% of v ref . 4. these are dc test criteria. the ac v ih / v il levels are defined separately to measure timing parameters. 5. overshoot: v ih (ac) v ddq + 0.5 v for t t khkh /2 undershoot: v il (ac) ? 0.5 v for t t khkh/ 2 during normal operation, v ih(dc) must not exceed v ddq and v il(dc) must not be lower than v ss.
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 15 of 29 dec. 01, 2014 dc characteristics (t a = -40 to +85 c, v dd = 1.8v 0.1v, v ddq = 1.5v, v ref = 0.75v) parameter symbol test condition min. max. uni t notes 450mhz 400mhz operating supply i dd (x36) 770 710 ma 1,2,3 current (x18) 600 550 (write / read) standby supply i sb1 (x36) 370 350 ma 2,4,5 current (x18) 320 310 (nop) input leakage current i li -2 2 output leakage current i lo -5 5 output high voltage v oh (low) |i oh | 0.1 ma v ddq ? 0.2 v ddq v 8 v oh note 6 v ddq /2 ? 0.12 v ddq /2 + 0.12 v 8 output low voltage v ol (low) i ol 0.1 ma v ss 0.2 v 8 v ol note 7 v ddq /2 ? 0.12 v ddq /2 + 0.12 v 8 notes: 1. all inputs (except zq, v ref ) are held at either v ih or v il . 2. i out = 0 ma. v dd = v dd max, t khkh = t khkh min. 3. operating supply currents (i dd ) are measured at 100% bus utilization. i dd of ddr family is current of device with 100% write cycle (if i dd (write) > i dd (read)) or 100% read cycle (if i dd (write) < i dd (read)). 4. all address / data inputs are static at either v in > v ih or v in < v il . 5. reference value. (condition = nop currents are valid when entering nop after all pending read and write cycles are completed. ) 6. outputs are impedance-controlled. |i oh | = (v ddq /2)/(rq/5) for values of 17 5 rq 350 . 7. outputs are impedance-controlled. i ol = (v ddq /2)/(rq/5) for values of 175 rq 350 . 8. ac load current is higher than the shown dc valu es. ac i/o curves are available upon request. 9. 0 v in v ddq for all input balls (except v ref , zq, tck, tms, tdi ball). 10. 0 v out v ddq (except tdo ball), output disabled.
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 16 of 29 dec. 01, 2014 thermal resistance parameter symbol airflow typ unit test condition notes junction to ambient ja 1 m/s 13 c/w eia/jedec jesd51 1 junction to case jc - 6.3 notes: 1. these parameters are calculated under the condition. these are reference values. 2. tj = ta + ja pd tj = tc + jc pd where tj : junction temperature when the device has achiev ed a steady-state after application of pd (c) ta :ambient temperature (c) tc :temperature of external surfa ce of the package or case (c) ja :thermal resistance from junction-to-ambient (c/w) jc :thermal resistance from junctio n-to-case (package) (c/w) pd :power dissipation that produced change in junction temperature (w) (cf.jesd51-2a) capacitance (t a = +25 c, frequency = 1.0mhz, v dd = 1.8v, v ddq = 1.5v) parameter symbol min typ max unit test condition note input capacitance (sa, /r, /w, /bw) c in - 4 5 pf v in = 0 v 1,2 clock input capacitance (k, /k, c, /c) c clk - 4 5 pf v clk = 0 v 1,2 output capacitance (dq, cq, /cq) c i/o - 5 6 pf v i/o = 0 v 1,2 notes: 1. these parameters are sampled and not 100% tested. 2. except jtag (tck, tms, tdi, tdo) pins. ac test conditions input waveform (rise/fall time 0.3 ns) 1.25v 0.25v 0.75v 0.75v test points output waveform v ddq /2 test points v ddq /2
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 17 of 29 dec. 01, 2014 output load conditions 50 zq q v ref 250 z 0 = 50 sram v ddq / 2 = 0.75v v ddq / 2 = 0.75v v dd v ddq v ss 1.8v0.1v 1.5v ac operating conditions parameter symbol min typ max unit notes input high voltage v ih (ac) v ref + 0.2 - - v 1,2,3,4 input low voltage v il (ac) - - v ref ? 0.2 v 1,2,3,4 notes: 1. all voltages referenced to v ss (gnd). during normal operation, v ddq must not exceed v dd . 2. these conditions are for ac functions only, not for ac parameter test. 3. overshoot: v ih (ac) v ddq + 0.5 v for t t khkh /2 undershoot: v il (ac) ? 0.5 v for t t khkh /2 control input signals may not have pulse widths less than t khkl (min) or operate at cycle rates less than t khkh (min). 4. to maintain a valid level, the transitioning edge of the input must: a. sustain a constant slew rate from the curren t ac level through the target ac level, v il (ac) or v ih (ac) . b. reach at least the target ac level. c. after the ac target level is re ached, continue to maintain at least the target dc level, v il (dc) or v ih (dc) .
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 18 of 29 dec. 01, 2014 ac characteristics (t a = -40 to +85 c, v dd = 1.8v 0.1v, v ddq = 1.5v, v ref = 0.75v) parameter symbol 450mhz 400mhz unit notes min max min max clock average clock cycle time (k, /k, c, /c) t khkh 2.20 4.00 2.50 4.00 ns clock high time (k, /k) t khkl 0.40 - 0.40 - cycle clock low time (k, /k) t klkh 0.40 - 0.40 - cycle clock to /clock (k to /k) t kh/kh 0.425 - 0.425 - cycle /clock to clock (/k to k) t /khkh 0.425 - 0.425 - cycle pll timing clock phase jitter (k, /k) t kc var - 0.15 - 0.20 ns 3 lock time (k) t kc lock 20 - 20 - us 2 k static to pll reset t kc reset 30 - 30 - ns 5 output times k, /k high to output valid t chqv - 0.45 - 0.45 ns k, /k high to output hold t chqx -0.45 - -0.45 - ns k, /k high to echo clock valid t chcqv - 0.45 - 0.45 ns k, /k high to echo clock hold t chcqx -0.45 - -0.45 - ns cq, /cq high to output valid t cqhqv - 0.15 - 0.20 ns 5 cq, /cq high to output hold t cqhqx -0.15 -0.20 ns 5 clock to /clock (cq to /cq) t cqh/cqh 0.85 - 1.00 - ns 5 /clock to clock (/cq to cq) t /cqhcqh 0.85 - 1.00 - ns 5 k, /k high to output high-z t chqz - 0.45 - 0.45 ns 4 k, /k high to output low-z t chqx1 -0.45 - -0.45 - ns 4 cq high to qvld valid t qvld -0.15 0.15 -0.20 0.20 ns 5 setup times address valid to k rising edge t avkh 0.40 - 0.40 - ns 1 control inputs valid to k rising edge t ivkh 0.40 - 0.40 - ns 1 data-in valid to k, /k rising edge t dvkh 0.25 - 0.28 - ns 1 hold times k rising edge to address hold t khax 0.40 - 0.40 - ns 1 k rising edge to control inputs hold t khix 0.40 - 0.40 - ns 1 k, /k rising edge to data-in hold t khdx 0.25 - 0.28 - ns 1
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 19 of 29 dec. 01, 2014 notes: 1. this is a synchronous device. all addresses, data an d control lines must meet th e specified setup and hold times for all latching clock edges. 2. v dd and v ddq slew rate must be less than 0.1 v dc per 50 ns for pll lock retention. pll lock time begins once v dd , v ddq and input clock are stable. it is recommended that the device is kept inactive during these cycles. 3. clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 4. transitions are measured 100 mv from steady-state voltage. 5. these parameters are only guaranteed by design and are not tested in production. remarks: 1. test conditions as specified with the output loading as shown in ac test conditions unless otherwise noted. 2. control input signals may not be operated with pulse widths less than t khkl (min). 3. v ddq is +1.5 v dc. v ref is +0.75 v dc. 4. control signals are /ld and r-/w. setup and hold times of /bwx signals must be the same as those of data-in signals. 5. in the case of running frequency between 400mhz and 450mhz, all the ac/dc parameters follow 450mhz.
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 20 of 29 dec. 01, 2014 read and write timing 1. q00 refers to output from address a0. q01 refers to output from the next internal burst address following a0, i.e., a0+1. 2. in this example, if address a8 = a7, then data q80 = d70, q81 = d71, etc. write data is forwarded immediately as read results. 3. to control read and write operations, /bw signals must operate at the same timing as data-in signals. 4. it recommends two nop cycles during transition from read to write cycle for correct device operation. 1 23 456 78 90 11 1 2 13 1 k / , k p o n d a e r ) 2 f o t s r u b ( d a e r ) 2 f o t s r u b ( e t i r w ) 2 f o t s r u b ( p o n p o n w / - r : d l / a s k k / e t i r w ) 2 f o t s r u b ( d a e r ) 2 f o t s r u b ( 0 a 0 0 1 0 1 0 1 0 x 1 x 1 0 0 2 a 6 a 4 a d a e r ) 2 f o t s r u b ( d a e r ) 2 f o t s r u b ( e t i r w ) 2 f o t s r u b ( e t i r w ) 2 f o t s r u b ( 1 0 1 0 0 0 0 0 d a e r ) 2 f o t s r u b ( 1 0 1 a 3 a 5 a 8 a 7 a 9 a 0 0 q 1 x q 1 0 q 0 1 q 1 1 q 0 2 q 1 2 q 0 3 q 1 3 q 0 x q 2 x q q d q c q c / d l v q t khkl t klkh t kh/kh t /khkh t ivkh t khix t khkh t avkh t khax 0 4 d1 4 d0 5 d 1 5 d0 6 d1 6 d0 7 d1 7 d t chqz -t chqx1 t chqv -t chqx t chqv -t chqx t cqhqv -t cqhqx t khdx t dvkh t khdx t dvkh t chcqv -t chcqx t chcqv -t chcqx t qvld -t qvld t qvld -t qvld
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 21 of 29 dec. 01, 2014 jtag specification these products support a limited set of jtag functions as in ieee standard 1149.1. disabling the test access port it is possible to use this device without utilizing the tap. to disable the tap controller without interfering with normal operation of the device, tck must be tied to v ss to preclude mid level inputs. tdi and tms are internally pulled up and may be unconnected, or may be connected to v dd through a pull up resistor. tdo should be left unconnected. test access port (tap) pins notes: the device does not have trst (tap reset). the test-log ic reset state is entered while tms is held high for five rising edges of tck. the tap contro ller state is also reset on sram power-up. tap dc operating characteristics (t a = -40 to +85 c , v dd = 1.8v 0.1v) parameter symbol min typ max unit notes input high voltage v ih +1.3 - v dd + 0.3 v input low voltage v il -0.3 - +0.5 v input leakage current i li -5.0 - +5.0 v in v dd output leakage current i lo -5.0 - +5.0 a 0 v v in v dd , output disabled output low voltage v ol1 - - 0.2 v i olc = 100 a v ol2 - - 0.4 v i olt = 2 ma output high voltage v oh1 1.6 - - v |i ohc | = 100 a v oh2 1.4 - - v |i oht | = 2 ma notes: 1. all voltages referenced to v ss (gnd). 2. at power-up, v dd and v ddq are assumed to be a linear ramp from 0v to v dd (min.) or v ddq (min.) within 200ms. during this time, v ddq < v dd and v ih < v ddq . during normal operation, v ddq must not exceed v dd . symbol i/o pin assignments description notes tck 2r test clock input. all inputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms 10r test mode select. this is the command input for the tap controller state machine. tdi 11r test data input. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is determined by the state of the t ap controller state machine and the instruction that is currently loaded in the tap instruction. tdo 1r test data output. output changes in response to the falling edge of tck. this is the output side of the serial registers placed between tdi and tdo.
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 22 of 29 dec. 01, 2014 tap ac test conditions parameter symbol conditions unit notes input timing measurement reference levels v ref 0.9 v input pulse levels v il , v ih 0 to 1.8 v input rise/fall time tr, tf 1.0 ns output timing measurement reference levels 0.9 v test load termination supply voltage (v tt ) 0.9 v output load see figures input waveform 1.8v 0v 0.9v 0.9v test points output waveform 0.9v test points 0.9v output load condition external load at test 50 v tt = 0.9v tdo z 0 = 50 dut 20pf
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 23 of 29 dec. 01, 2014 tap ac operating characteristics (t a = -40 to +85 c , v dd = 1.8v 0.1v) parameter symbol min typ max unit notes test clock (tck) cycle time t thth 50 - - ns tck high pulse width t thtl 20 - - ns tck low pulse width t tlth 20 - - ns test mode select (tms) setup t mvth 5 - - ns tms hold t thmx 5 - - ns capture setup t cs 5 - - ns capture hold t ch 5 - - ns tdi valid to tck high t dvth 5 - - ns tck high to tdi invalid t thdx 5 - - ns tck low to tdo unknown t tlqx 0 - - ns tck low to tdo valid t tlqv - - 10 ns notes: 1. t cs + t ch defines the minimum pause in ram i/o pad transitions to assure pad data capture.
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 24 of 29 dec. 01, 2014 tap controller timing diagram tck tdi tms tdo pi (sram) thtl thth tlth mvth thmx dvth thdx cs ch tlqv tlqx ttt tt t t t t tt test access port registers register name length symbol notes instruction register 3 bits ir [2:0] bypass register 1 bits bp id register 32 bits id [31:0] boundary scan register 109 bit bs [109:1]
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 25 of 29 dec. 01, 2014 tap controller instruction set ir2 ir1 ir0 instruction description notes 0 0 0 extest the extest instruction allows circuitry external to the component package to be tested. boundary scan register cells at output balls are used to apply test vectors, whil e those at input balls capture test results. typically, the first test vector to be applied using the extest instruction will be shift ed into the boundary scan register using the preload instruction. thus, during the update-ir state of extest, the output driver is turned on and the preload data is driven onto the output balls. 1,2,3,4 0 0 1 idcode the idcode instruction causes t he id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi and tdo balls in shift-dr mode. the idcode instruction is the defau lt instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. 0 1 0 sample-z if the sample-z instruction is loaded in the instruction register, all ram outputs are forced to an inactive drive state (high-z), moving the tap controller into the captur e-dr state loads the data in the rams input into the boundary scan register, and the boundary scan register is connected between tdi and tdo when the tap controller is moved to the shift-dr state. 3,4 0 1 1 reserved the reserved instruction is not implemented but is reserved for future use. do not use this instruction. 1 0 0 sample (/preload) when the sample instruction is load ed in the instruction register, moving the tap controller into t he capture-dr stat e loads the data in the rams input and i/o buffers in to the boundary scan register. because the ram clock(s) are in dependent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e., in a metastable state). although allowing the ta p to sample metastable input will not harm the device, repeatable results cannot be expected. moving the controller to shift-dr state then places the boundary scan register between the tdi and tdo balls. 3,4 1 0 1 reserved the reserved instruction is not implemented but is reserved for future use. do not use this instruction. 1 1 0 reserved the reserved instruction is not implemented but is reserved for future use. do not use this instruction. 1 1 1 bypass the bypass instruction is loaded in the instruction register when the bypass register is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the board level scan path to be s hortened to facilitate testing of other devices in the scan path. notes: 1. data in output register is not guarant eed if extest instruction is loaded. 2. after performing extest, power-up conditions are required in order to return part to normal operation. 3. ram input signals must be stabilized for long enough to meet the taps input data capture setup plus hold time (t cs plus t ch ). the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary scan register. 4. clock recovery initialization cycles are required after boundary scan.
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 26 of 29 dec. 01, 2014 boundary scan order bit# ball id signal names bit# ball id signal names bit# ball id signal names x18 x36 x18 x36 x18 x36 1 6r nc nc 38 9e nc nc 75 2d nc dq29 2 6p qvld qvld 39 10c dq7 dq17 76 2e nc nc 3 6n sa sa 40 11d nc dq16 77 1e nc nc 4 7p sa sa 41 9c nc nc 78 2f dq12 dq30 5 7n sa sa 42 9d nc nc 79 3f nc dq21 6 7r sa sa 43 11b dq8 dq8 80 1g nc nc 7 8r sa sa 44 11c nc dq7 81 1f nc nc 8 8p sa sa 45 9b nc nc 82 3g dq13 dq22 9 9r sa sa 46 10b nc nc 83 2g nc dq31 10 11p dq0 dq0 47 11a cq cq 84 1h /doff /doff 11 10p nc dq9 48 10a sa nc 85 1j nc nc 12 10n nc nc 49 9a sa sa 86 2j nc nc 13 9p nc nc 50 8b sa sa 87 3k dq14 dq23 14 10m dq1 dq11 51 7c sa sa 88 3j nc dq32 15 11n nc dq10 52 6c nc nc 89 2k nc nc 16 9m nc nc 53 8a /ld /ld 90 1k nc nc 17 9n nc nc 54 7a nc /bw1 91 2l dq15 dq33 18 11l dq2 dq2 55 7b /bw0 /bw0 92 3l nc dq24 19 11m nc dq1 56 6b k k 93 1m nc nc 20 9l nc nc 57 6a /k /k 94 1l nc nc 21 10l nc nc 58 5b nc /bw3 95 3n dq16 dq25 22 11k dq3 dq3 59 5a /bw1 /bw2 96 3m nc dq34 23 10k nc dq12 60 4a r-/w r-/w 97 1n nc nc 24 9j nc nc 61 5c sa sa 98 2m nc nc 25 9k nc nc 62 4b sa sa 99 3p dq17 dq26 26 10j dq4 dq13 63 3a sa sa 100 2n nc dq35 27 11j nc dq4 64 2a nc nc 101 2p nc nc 28 11h zq zq 65 1a /cq /cq 102 1p nc nc 29 10g nc nc 66 2b dq9 dq27 103 3r sa sa 30 9g nc nc 67 3b nc dq18 104 4r sa sa 31 11f dq5 dq5 68 1c nc nc 105 4p sa sa 32 11g nc dq14 69 1b nc nc 106 5p sa sa 33 9f nc nc 70 3d dq10 dq19 107 5n sa sa 34 10f nc nc 71 3c nc dq28 108 5r sa sa 35 11e dq6 dq6 72 1d nc nc 109 - internal internal 36 10e nc dq15 73 2c nc nc 37 10d nc nc 74 3e dq11 dq20 notes: in boundary scan mode, 1. clock balls (k, /k) are referenced to each other and must be at opposite logic levels for reliable operation. 2. cq and /cq data are synchronized to th e k clock (except extest, sample-z).
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 27 of 29 dec. 01, 2014 id register start bit (0) # 31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 rmqcha3636dgba00001000001001011010010001000111 rmqcha3618dgba00001000001001011011010001000111 (31:28) number revision type number (27:12) vendor jedec code (11:1) tap controller state diagram notes: the value adjacent to each state transition in this figure represents the signal present at tms at the time of a rising edge at tck. no matter what the original state of the controller, it will enter test-logic-reset when tms is held high for at least five rising edges of tck. capture ir shift ir exit1 ir pause ir exit2 ir update ir 0 0 1 0 1 1 0 1 0 0 1 select dr scan 0 0 1 0 1 1 0 1 0 0 1 run test/idle 0 10 1 1 1 0 0 11 test logic reset select ir scan capture dr shift dr exit1 dr pause dr exit2 dr update dr
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 28 of 29 dec. 01, 2014 package dimensions 165-pin fbga (13 x 15 x 1.4 mm) previous code ] . p y t [ s s a m e d o c s a s e n e r e d o c e g a k c a p a t i e j 0.5g a - g h f 5 6 1 0 0 . 1 - 5 1 x 3 1 - 5 6 1 a g b l - p plbg0165fe-a 0.2 0.6 0.5 0.45 max nom min dimension in millimeters symbol reference 13.0 d 15.0 e 1.4 a 0.41 0.36 0.31 x 1.0 e 0.15 y a 1 b z d 1.5 z e 0.5 13.1 15.1 12.9 14.9 b a s s m s y ab index mark index mark (laser mark) 10 11 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r e d a 1 a z d z e e e >
rmqcha3636dgba, rmqcha3618dgba preliminary datasheet r10ds0240ej0002 rev.0.02 page 29 of 29 dec. 01, 2014 revision history rmqcha3 636dgba, rmqcha3618dgba rev. date description page summary rev.0.01 ?14.04.25 - new preliminary datasheet. rev.0.02 ?14.12.01 p.15, 16 modify the ?supply current? and ?thermal resistance?. qdr rams and quad data rate rams comprise a new family of products developed by cypress semiconductor, and renesas electronics corporation. http://www.qdrconsortium.org/ the information contained herein is subject to change without notice.
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